One type of prior art non-volatile computer memory is the Erasable Programmable Read-Only Memory ("EPROM"). The EPROM can be programmed by a user. Once programmed, the EPROM retains its data until erased. Ultraviolet light erasure of the EPROM erases the entire contents of the memory array. The memory array may then be reprogrammed with new data.
The prior EPROM typically includes a decoding circuit to address the memory array of the device. The decoding circuit receives addresses from address input pins of the EPROM. Data stored in the EPROM at the applied address can then be read via the output pins of the EPROM.
The prior EPROM also typically includes redundant memory cells. The redundant memory cells are used to replace defective cells of the main memory array. The redundant memory cells are also arranged into rows and columns and are therefore referred to as redundant memory array. When a memory cell in a column or row of the main memory array is found defective, a redundant column or row of the redundant memory array is used to replace the defective column or row in the main memory array.
In order to replace a defective memory column or row in the main memory array with a redundant memory column or row, the defective column or row needs to be disconnected from being accessed when addressed. FIG. 1 illustrates one prior art scheme of disconnecting the defective column or row in the main memory array.
As can be seen from FIG. 1, each of the memory elements (i.e., memory row or column) of main memory array 11 of EPROM 10 is connected to a main select circuit 13 via one of fuse elements 17 through 18n. When one memory element in main memory array 11 is found defective, its associated one of fuse elements 17-18n will be blown with a laser beam such that the access to the defective memory element in main memory array 11 is disabled. For example, when the memory element that is connected to fuse element 17 is found defective, fuse element 17 will then be blown to disable the access to that defective memory element from main decoder 15 and main select circuit 13.
Disadvantages are, however, associated with this prior an scheme. One disadvantage is that the fuse elements typically require relatively large die space in the EPROM. This is due to the laser alignment requirements. In addition, the use of laser beam to blow the fuse elements typically causes the fabrication cost of the prior EPROM to increase significantly. Moreover, the fuse elements typically introduce parasitic resistance in the access path of the memory cells.
A prior solution to solving this problem is to dynamically disable the main decoder or the main select circuit for the main memory array whenever the defective memory element is addressed. FIG. 2 illustrates one such prior scheme of dynamically disabling the main select circuit whenever the defective memory element of the main memory array is addressed.
As can be seen from FIG. 2, prior EPROM 20 includes a main decoder 25, a main select circuit 23, and a main memory array 21. Prior EPROM 20 also includes a redundant memory array 22, a redundant select circuit 24, and a redundant decoder 26. Redundant decoder 26 includes in addition to other circuitry, a number of storage circuits 26a through 26n, each being used to activate one redundant element of redundant memory array 22 to replace a defective memory element of main memory array 21 . Each of storage circuits 26a-26n includes (1) a number of nonvolatile storage elements to store an address of a defective memory element of main memory array 21 and (2) a comparator for comparing the external addresses applied with the address stored in the nonvolatile storage elements of that storage circuit.
When a defective memory element in main memory array 21 is discovered, a redundant memory element is activated to replace the defective memory element. This is done by storing the address of the defective memory element in the nonvolatile storage elements of a storage circuit associated with that redundant memory element. A comparison with the stored address is made every time EPROM 20 is addressed to determine whether the defective memory element is addressed. If so, the comparator generates an enable/disable signal to cause redundant select circuit 24 to activate the associated redundant memory element. In addition, the enable/disable signal is also applied to main select circuit 23 to disable the entire main select circuit. Main select circuit 23 includes an AND gate for each of the memory elements of main memory array 21 and a NOR gate 29 coupled to receive the enable/disable signal from each of storage circuits 26a-26n. When any one of storage circuits 26a-26n generates the enable/disable signal, the entire circuit of main select circuit 23 is disabled from accessing main memory array 21.
One disadvantage of this prior scheme is the slower access to the EPROM when a defective memory element is addressed. This is due to the fact that the access to redundant memory array 22 has to wait until the entire circuit of main select circuit 23 is disabled. This typically requires NOR gate 29 to have relatively large driving capability in order to disable the entire circuit of main select circuit 23. The larger the driving capability the NOR gate is required to have, the slower the circuit is. In addition, the relatively large driving ability of NOR gate 29 also requires the NOR gate to be made large, thus occupying relatively large die space within the prior EPROM.